The present invention relates to a duty detecting circuit and a duty cycle corrector including the same, and more particularly, to a technology that can exactly measure a duty distortion degree at a time.
In semiconductor devices such as semiconductor memory devices designed to operate based on a clock, it is very important to exactly control a duty cycle of the clock. A 50% clock duty ratio means that a “high” level period is equal to a “low” level period in the clock.
A semiconductor memory device must input and output data exactly in synchronization with rising and falling edges of the clock. If the clock duty ratio is not exactly 50%, a timing between the rising edge and the falling edge is distorted so that data are not outputted and inputted at an accurate timing. Therefore, the semiconductor memory device uses a duty cycle corrector (DCC) to match the clock duty ratio to 50%.
Conventional duty cycle correctors have many limitations in correcting the clock duty cycle.
First, the conventional duty cycle correctors generate an up/down signal by comparing a high pulse width with a low pulse width of the clock and correct the duty ratio little by little according to the up/down signal. Such duty cycle correctors perform several comparison operations until completion of the duty cycle correction, which will increase a locking time.
Second, digital duty cycle correctors have difficulty in measuring an accurate duty ratio because of their own offset.
Third, there is a limitation in a frequency range of an input clock whose duty cycle will be corrected.